Journal #1

I’ve always been meaning to keep a journal. I have lots of things that I’d like to write down, to remember, but I never manage to get over the activation threshold for it. Well, after 4am rolls around, I usually get an urge to write something, but I’m usually also starting to feel tired and lazy. Right now, it’s just after 7am, and I’m still not really tired.

Today was pretty typical. Rolled in to work at 4pm, coffee in hand. Yesterday, I finished implementing buses in Verilog-A. (A “bus” is pretty much just an array of nodes.) This was a huge milestone: I think I’ve been working on this one task for about a month. (1/3 of the time that I’ve spent at Upverter so far.) However, I quickly realized that buses aren’t very useful without for loops to operate on them. So while Mike was happy that I finished this task, he was less happy that we can’t ship this product yet.

I Heart Upverter By the way, I’ve been working at Upverter since October. Before that, I was working at RIM as an embedded firmware developer, specifically dealing with audio hardware. If you own a Blackberry from the past couple of years, I’m the one to blame if it doesn’t detect your wired headset correctly when you insert it or press a button. I also did some work on plumbing for some DSPs. Apparently, they really liked me at RIM, (in my performance review, they said that I “challenge others to do a better job”) but they weren’t planning to give me any real responsibility for at least another 2-3 years, which was way too far away for me. Also, they had this thing about coming in to work by 10am, which left me in a zombie-like state for most of the day.

Oh right, Upverter. I’m working on their simulation product. At the moment, you can go to the site, build a simple circuit, (most of the parts won’t be simulatable, but you can do RLC filters for sure!) press a button and get the voltages at each node and the current from your source. It’s… a little useless right now. But that’s where I come in: I’m working on a Verilog-A extension to the simulator. Part of it is open source too! So you can write a model for a circuit in Verilog-A (Verilog-A is the analog-only subset of the complete language) and use it the simulator as if it were any other standard component like a resistor or capacitor. For example, I could write a model for a 555 timer and then attach it to the 555 timers that people use in their designs on the site. Then we can simulate them!

Some of the code that I have to deal with is pretty terrible though. The project is basically a fork of some French guy’s, in which he decided to use XML as the syntax for a horribly incomplete, and hostile “programming language” for outputting the results of the parsed Verilog-A code. Here’s an example of something you might see:

<admst:template match="node">
    <admst:text format="Node: %(.)\n"/>
</admst:template>
<admst:for-each select="node[grounded='no']">
    <admst:apply-templates match="%(datatypename)" select="."/>
</admst:for-each>

I don’t really care to explain all of that. Templates are kind of like functions, except that they can only take one argument (although, I realized that I could pass a “list” object, but you have to explicitly create them yourself) and while they do technically support returning things, it seems you can only return strings, not objects. Also, XML! It’s incredibly inefficient to use. Every command in this language has to start with “admst:” and everything either needs to be closed, or you can to say it’s a void tag. Argh. When you have a screen full of this, the closing tags become so noisy that I had to go out of my way to reduce that noise. I wrote an extension to nxml-mode in Emacs, which hides the closing tags, and has significantly improved the readability of the code. You can use it for any general XML too, which is nice.

The implementation of the language itself is also next to impossible to maintain or understand. For some reason, the French guy (or, “that damned French guy”, as I often refer to him) decided to automatically generate the yacc code to parse the Verilog-A and the language. Not only that, but the Perl script that does this (which does not ‘use strict’ and is so horribly written that I can only conclude that it’s a form of intentional obfuscation) generates parts of itself!

map{eval("sub x$_ {\&checkargument(\@_); shift->getAttribute(\"$_\");}");} qw(name path datatypefamily datatypename default info element attribute format);

Okay, I’m starting to ramble, so let’s wrap this up. I can’t say for sure if I’ll commit to a journal. I’ve tried in the past, and it’s never worked out. I’ve also been a little reluctant to get too free with what I say on my site. My parents have commented on coming here before, so I’ll have to keep that in mind. Today’s entry got a little out of hand because I was trying to cover some background, and then I started raging about this terrible XML language. I didn’t get to half of what I meant to talk about just for today, but this page is already a giant wall of text. Also, my battery’s going to die soon, and it’s coming up on 8am and I should sleep.

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